Aspects of the present invention relate generally to the field of circuit design and test, and more specifically to compression of data in emulation systems for functional verification of circuit designs.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries. An electronic design automation (EDA) tool may facilitate the design by allowing a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are performed on the layout using a set of testing, simulation, analysis and validation tools. For example, hardware designers may employ a hardware based verification platform to perform certain testing operations. Hardware verification platforms can enable testing of the various components of the design, which facilitates design analysis and debugging. Multiple aspects of the hardware design typically may be tested. For example, a hardware design may undergo architectural simulation and analysis and debugging where the functionality of each of the components being implemented in the design is tested, for example, with transaction level modeling (TLM) or bus functional modeling. The hardware design may additionally undergo circuit simulation and analysis where the signals between components are tested, for example using register transition level (RTL) analysis.
Other steps may include system simulation, for example to model the components of a system together, and system and software emulation, for example to model execution of the hardware and software elements executing on a modeled system. A common method of design verification is to use hardware emulators to emulate the circuit design prior to physically manufacturing the integrated circuit. Hardware functional verification systems typically utilize arrays of processing devices or programmable logic devices, and to verify circuit designs. Processor-based emulators sequentially evaluate the design under verification, starting at the inputs and proceeding to the outputs, allowing engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate and manufacture the electronic hardware.
Additionally, during execution of the emulation, a large amount of test results such as logic waveforms and other data will be generated. The quantity of data can be so large that the time to transfer the data to a host workstation or to storage can significantly impact the performance perceived by the user.
Accordingly there is a need in the art for an emulation system that provides flexible access to the emulation processes and test logic and further provides for compression of the generated test data.